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LTP
Load TREG and Store PREG in Accumulator
7-98
Syntax LTP
dma
Direct addressing
LTP
ind
[, AR
n
] Indirect addressing
Operands dma: 7 LSBs of the data-memory address
n: Value from 0 to 7 designating the next auxiliary register
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
LTP
dma
1514131211109876543210
0
11100010 dma
LTP
ind
[, AR
n
]
1514131211109876543210
0
11100011 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
Execution Increment PC, then ...
(data-memory address) → TREG
shifted (PREG) → ACC
Status Bits
Affected by
PM
Description The TREG is loaded with the content of the addressed data-memory location,
and the PREG value is stored in the accumulator. The shift at the output of the
PREG is controlled by the PM status bits.
Words 1
Cycles for a Single LTP Instruction
Program
Operand ROM DARAM SARAM External
DARAM 1 1 1 1+p
SARAM 1 1 1, 2
†
1+p
External 1+d 1+d 1+d 2+d+p
†
If the operand and the code are in the same SARAM block
Opcode
Cycles