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’C209 Versus Other ’C2xx Devices
11-3
TMS320C209
Memory and I/O Spaces:
The I/O addresses of the peripheral registers are different on the
’C209.
The ’C209 does not support the ’C2xx HOLD operation.
Interrupts:
The ’C209 has four maskable interrupt lines, none of them shared.
The other devices have six interrupt lines, one shared by the INT2
and
INT3
pins.
The ’C209 does not have an interrupt control register (ICR) because
INT2
and INT3 have their own interrupt lines.
Although the interrupt flag register (IFR) and interrupt mask register
(IMR) are used in the same way on all ’C2xx device, the ’C209 has
fewer flag and mask bits because it does not have serial ports.
On the ’C209, interrupts INT2 and INT3 have their own interrupt lines
and, thus, have their own interrupt vectors. On other ’C2xx devices,
INT2
and INT3 share an interrupt line and, thus, share one interrupt
vector.
The ’C209 has an interrupt acknowledge pin (IACK), which allows ex-
ternal detection of when an interrupt has been acknowledged.
The ’C209 has two pins for reset: RS and RS; other ’C2xx devices
have only RS
.
11.1.3 Where to Find the Information You Need About the TMS320C209
For information about: Look here:
Assembly language instructions Chapter 7,
Assembly Language
Instructions
Clock generator Main description Chapter 8,
On-Chip Peripherals
Options and configuration Subsection 11.4.1 (page 11-14)
CPU Chapter 3,
Central Processing Unit
Data-address generation Chapter 6,
Addressing Modes
I/O Space Main description Chapter 4,
Memory
Effect of READY pin Section 11.2 (page 11-5)
Control register locations Table 11–3 (page 11-9)