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F-23
Glossary
TIM bit:
Transmit interrupt mask bit
. Bit 8 of the asynchronous serial port
control register (ASPCR); enables or disables transmit interrupts of the
asynchronous serial port.
TIM register: See
timer counter register (TIM)
.
timer counter register (TIM): A 16-bit memory-mapped register that holds
the main count for the on-chip timer. See also
timer prescaler counter
(PSC)
.
timer divide-down register (TDDR): Bits 3–0 of the timer control register
(TCR); specifies the timer divide-down period for the on-chip timer. When
the timer prescaler counter (PSC) decrements past zero, the PSC is
loaded with the value in the TDDR. See also
timer period register (PRD)
.
timer interrupt (TINT): See
TINT
.
timer period register (PRD): A 16-bit memory-mapped register that speci-
fies the main period for the on-chip timer. When the timer counter register
(TIM) is decremented past zero, the TIM is loaded with the value in the
PRD. See also
TDDR
.
timer prescaler counter (PSC): Bits 9–6 of the timer control register (TCR);
specifies the prescale count for the on-chip timer.
timer reload bit (TRB): Bit 5 of the timer control register (TCR); when TRB
is set, the timer counter register (TIM) is loaded with the value of the timer
period register (PRD), and the prescaler counter (PSC) is loaded with the
value of the timer divide-down register (TDDR).
timer stop status bit (TSS):
Bit 4 of the TCR. TSS is used to start and stop
the timer.
TINT:
Timer interrupt
. An interrupt generated by the timer on the next
CLKOUT1 cycle after the main counter (TIM register) decrements to 0
TOS:
Top of stack.
Top level of the 8-level last-in, first-out hardware stack.
TOUT:
Timer output pin.
Provides access to an output signal based on the
rate of the on-chip timer. On the next CLKOUT1 cycle after the main
counter (TIM register) decrements to 0, a signal is sent to TOUT.
transmit interrupt (asynchronous serial port): An interrupt (TXRXINT)
generated when the transmit register (ADTR) empties during transmis-
sion. This condition indicates that the ADTR is ready to accept a new
transmit character.
transmit interrupt (synchronous serial port): See
XINT
.
Glossary