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F-16
OV bit:
Overflow flag bit.
Bit 12 of status register ST0; indicates whether the
result of an arithmetic operation has exceeded the capacity of the accu-
mulator.
overflow (in a register): A condition in which the result of an arithmetic op-
eration exceeds the capacity of the register used to hold that result.
overflow (in the synchronous serial port): A condition in which the re-
ceive FIFO buffer of the port is full and another word is received in the
RSR. (None of the contents of the FIFO buffer are overwritten by this new
word.)
overflow mode: The mode in which an overflow in the accumulator will
cause the accumulator to be loaded with a preset value. If the overflow
is in the positive direction, the accumulator will be loaded with its most
positive number. If the overflow is in the negative direction, the accumu-
lator will be filled with its most negative number.
overrun: A condition in the receiver of the asynchronous serial port. Overrun
occurs when an unread character in the ADTR is overwritten by a new
character.
OVF bit:
Overflow bit (synchronous serial port).
Bit 7 of the synchronous se-
rial port control register (SSPCR); indicates when the receive FIFO buff-
er of the port is full and another word is received in the RSR. (None of
the contents of the FIFO buffer are overwritten by this new word.)
OVM bit:
Overflow mode bit.
Bit 11 of status register ST0; enables or dis-
ables overflow mode. See also
overflow mode
.
P
PAB: See
program address bus (PAB).
PAR:
Program address register.
A register that holds the address currently
being driven on the program address bus for as many cycles as it takes
to complete all memory operations scheduled for the current machine
cycle.
PC: See
program counter (PC).
PCB:
Printed circuit board
.
pending interrupt: A maskable interrupt that has been successfully re-
quested but is awaiting acknowledgement by the CPU.
period register: See
PRD
.
GlossaryGlossary