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SQRA
Square Value and Accumulate Previous Product
7-168
Syntax SQRA
dma
Direct addressing
SQRA
ind
[, AR
n
] Indirect addressing
Operands dma: 7 LSBs of the data-memory address
n: Value from 0 to 7 designating the next auxiliary register
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
SQRA
dma
1514131211109876543210
0
10100100 dma
SQRA
ind
[, AR
n
]
1514131211109876543210
0
10100101 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
Execution Increment PC, then ...
(ACC) + shifted (PREG) → ACC
(data-memory address) → TREG
(TREG) (data-memory address) → PREG
Status Bits
Affected by Affects
OVM and PM OV and C
Description The content of the PREG, shifted as defined by the PM status bits, is added
to the accumulator. Then the addressed data-memory value is loaded into the
TREG, squared, and stored in the PREG.
Words 1
Cycles for a Single SQRA Instruction
Program
Operand ROM DARAM SARAM External
DARAM 1 1 1 1+p
SARAM 1 1 1, 2
†
1+p
External 1+d 1+d 1+d 2+d+p
†
If the operand and the code are in the same SARAM block
Opcode
Cycles