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F-9
Glossary
FR0/FR1:
FIFO receive-interrupt bits
. Bits 8 and 9 of the synchronous serial
port control register (SSPCR); together they set an interrupt trigger
condition based on the number of words in the receive FIFO buffer.
frame synchronization (frame sync) mode: One of two modes in the syn-
chronous serial port that determine whether frame synchronization
pulses are necessary between consecutive data transfers. See also
burst mode
;
continuous mode
.
frame synchronization (frame sync) pulse: A pulse that signals the start
of a transmission from or reception into the synchronous serial port.
framing error: An error that occurs when a data character received by the
asynchronous serial port does not have a valid stop bit. See also
FE bit
.
FREE bit (asynchronous serial port): Bit 15 of the asynchronous serial
port control register (ASPCR); determines whether the port is in free-run
mode or an emulation mode. When FREE = 0, bit 14 (SOFT) determines
which emulation mode is selected.
FREE bit (synchronous serial port): Bit 15 of the synchronous serial port
control register (SSPCR); determines whether the port is in free-run
mode or an emulation mode. When FREE = 0, bit 14 (SOFT) determines
which emulation mode is selected.
FREE bit (timer): Bit 11 of the timer control register (TCR); determines
whether the timer is in free-run mode or an emulation mode. When
FREE = 0, bit 14 (SOFT) determines which emulation mode is selected.
FREE and SOFT are not available in the TCR of the ’C209.
FSM bit: Bit 1 of the synchronous serial port control register (SSPCR); deter-
mines the frame synchronization mode for the synchronous serial port.
See also
burst mode
;
continuous mode
.
FSR pin:
Receive frame synchronization pin.
This input pin accepts a frame
sync pulse that initiates the reception process of the synchronous serial
port.
FSX pin:
Transmit frame synchronization pin.
This input/output pin accepts/
generates a frame sync pulse that initiates the transmission process of
the synchronous serial port. If the port is configured for accepting an ex-
ternal frame sync pulse, the FSX pin receives the pulse. If the port is con-
figured for generating an internal frame sync pulse, the FSX pin transmits
the pulse.
FT0/FT1:
FIFO transmit-interrupt bits.
Bits 10 and 11 of the synchronous se-
rial port control register (SSPCR); together they set an interrupt trigger
condition based on the number of words in the transmit FIFO buffer.
Glossary