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Input Scaling Section
3-4
Shift count. The shifter can left-shift a 16-bit value by 0 to 16 bits. The size
of the shift (or the shift count) is obtained from one of two sources:
A constant embedded in the instruction word.
Putting the shift count in the
instruction word allows you to use specific data-scaling or alignment op-
erations customized for your program code.
The four LSBs of the temporary register (TREG).
The TREG-based shift
allows the data-scaling factor to be determined dynamically so that it can
be adapted to the system’s performance.
Sign-extension mode bit. For many but not all instructions, the sign-exten-
sion mode bit (SXM), bit 10 of status register ST1, determines whether the
CALU uses sign extension during its calculations. If SXM = 0, sign extension
is suppressed. If SXM = 1, the output of the input shifter is sign extended.
Figure 3–3 shows an example of an input value shifted left by 8 bits for
SXM = 0. The MSBs of the value passed to the CALU are zero filled.
Figure 3–4 shows the same shift but with SXM = 1. The value is sign extended
during the shift.
Figure 3–3. Operation of the Input Shifter for SXM = 0
Output value
after left shift of 8
(SXM = 0)
X X X X A F 1 1
16
Input shifter
accepting the
value
32
0 0 A F 1 1 0 0
A F 1 1
Figure 3–4. Operation of the Input Shifter for SXM = 1
Output value
after left shift of 8
(SXM = 1)
X X X X A F 1 1
16
Input shifter
accepting the
value
32
F F A F 1 1 0 0
A F 1 1