Filter
Top Products
Receiver Operation
9-24
9.6 Receiver Operation
Receiver operation is different in continuous and burst modes. The receiver
does not generate frame sync pulses; it always takes the frame sync pulse as
an input.
In selecting the proper receive mode, note that the mode for the receiver must
match the mode for the transmitter.
If all four words of the receive FIFO buffer have been filled, the buffer will not
accept additional words. If a fifth write is attempted, the overflow (OVF) bit of
the SSP control register (SSPCR) is set to 1.
9.6.1 Burst Mode Reception
Use burst mode receive to transfer short packets at rates lower than maximum
packet frequency.
This mode of operation offers these features:
The data packet is marked by the frame sync pulse on FSR.
Reception of data can be maintained continuously.
Generally, the transmit clock and the receive clock have the same source. This
allows each bit to be transmitted from another device on a rising edge of the
clock signal and received by the ’C2xx on the next falling edge of the clock sig-
nal.
The following events occur during a burst mode receive operation (see
Figure 9–8):
1) A frame sync pulse initiates the receive operation. This event is sampled
on the falling edge of CLKR.
2) On the next falling edge of CLKR after the falling edge of FSR, the first bit
(MSB) is shifted into the receive shift register (RSR).
3) The rest of the bits in the word are then shifted into RSR one at a time at
each consecutive falling edge of CLKR.
4) After all bits have been received, if the receive FIFO buffer is not full, the
contents of the RSR are copied into the receive FIFO buffer. If the FIFO
buffer becomes full during this operation, an interrupt (RINT) is sent to the
CPU, and the overflow bit (OVF) of the SSPCR is set.
5) The receive operation is started again after the next frame sync pulse.
However, the received word can be loaded into the FIFO buffer only if the
buffer is empty; otherwise, the word is lost.