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Components and Basic Operation
9-6
9.2.3 Interrupts
The synchronous serial port (SSP) has two hardware interrupts that let the pro-
cessor know when the FIFO buffers need to be serviced:
Transmit interrupts (XINTs) cause a branch to address 000Ah in program
space whenever the transmit-interrupt trigger condition is met. Set the trig-
ger condition by setting bits FT1 and FT0 in the SSPCR (see Table 9–3
on page 9-9). XINTs have a priority level of 8 (1 being highest).
Receive interrupts (RINTs) cause a branch to address 0008h in program
space whenever the receive-interrupt-trigger condition is met. The trigger
condition is selected by setting the FR1 and FR0 bits in the SSPCR (see
Table 9–4 on page 9-10). RINTs have a priority level of 7.
These are maskable interrupts controlled by the interrupt mask register (IMR)
and interrupt flag register (IFR).
Note:
To avoid a double interrupt from the SSP, clear the IFR bit (XINT or RINT)
in the corresponding interrupt service routine, just before returning from the
routine.
9.2.4 Basic Operation
Typically, transmitting a word through the serial port follows this four step
process:
1) Initialize the serial port to the desired configuration by writing to the
SSPCR.
2) Your software writes up to four words to the transmit FIFO buffer through
the SDTR.
3) The transmit FIFO buffer copies the earliest-written word to the transmit
shift register (XSR) when the XSR is empty.
4) The XSR shifts the data, bit-by-bit (MSB first), to the DX pin.
5) When the XSR empties, it signals the FIFO buffer, and then:
If the FIFO buffer is not empty, the process repeats from step 2.
If the FIFO buffer is empty (as specified by the FT1 and FT0 bits in the
SSPCR), it sends a transmit interrupt (XINT) to request more data,
and transmission stops.