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Reset Operation
5-33
Program Control
5.7 Reset Operation
Reset (RS) is a nonmaskable external interrupt that can be used at any time
to put the ’C2xx into a known state. Reset is the highest priority interrupt; no
other interrupt takes precedence over reset. Reset is typically applied after
power up when the machine is in an unknown state. Because the reset signal
aborts memory operations and initializes status bits, the system should be re-
initialized after each reset. The NMI interrupt can be used for soft resets be-
cause it neither aborts memory operations nor initializes status bits.
Driving RS
low causes the ’C2xx to terminate execution and affects various
registers and status bits. For correct system operation after power up, RS
must
be asserted for at least six clock cycles. The device latches the reset pulse and
generates an internal reset pulse long enough to ensure a device reset. The
device fetches its first instruction 16 cycles after the rising edge of RS
. Proces-
sor execution begins at location 0000h, which normally contains a branch
instruction to the system initialization routine.
When the ’C2xx receives a reset signal, the following actions take place:
Program-control features:
The program counter is cleared to 0 (however, the address bus,
A15–A0, is unknown while RS
is low).
Status bits in registers ST0 and ST1 are loaded with their reset values:
OV = 0, INTM = 1, CNF = 0, SXM = 1, C = 1, XF= 1 and PM = 00.
(The other status bits remain undefined and should be initialized by a
reset.)
The INTM (interrupt mode) bit is set to 1, disabling all maskable inter-
rupts. (RS
and NMI are not maskable.) Also, the interrupt flag register
(IFR), interrupt mask register (IMR), and interrupt control register
(ICR) are cleared.
The MODE bit of the interrupt control register (ICR) is set to 0 so that
the HOLD
/INT1 pin is both negative- and positive-edge sensitive.
The repeat counter (RPTC) is cleared.
Memory and I/O spaces:
A logic 0 is loaded into the CNF (configuration control) bit in status reg-
ister ST1, mapping dual-access RAM block B0 into data space.
The global memory allocation register (GREG) is cleared to make all
memory local.
The wait-state generator is set to provide the maximum number of wait
states for external memory and I/O accesses.