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Instruction Set Comparison Table
B-29
TMS320C1x/C2x/C2xx/C5x Instruction Set Comparison
Syntax
Description5x2xx2x1x
SACH
dma
[
, shift
]
SACH {
ind
} [
, shift
[
, next ARP
]]
√
√
√
√
√
√
√
√
Store High Accumulator With Shift
Copy the contents of the accumulator into a shifter.
Shift the entire contents 0, 1, or 4 bits (TMS320C1x) or
from 0 to 7 bits (TMS320C2x/2xx/5x), and then copy
the 16 MSBs of the shifted value into the addressed
data-memory location. The accumulator is not af-
fected.
SACL
dma
SACL
dma
[
, shift
]
SACL {
ind
} [
, shift
[
, next ARP
]]
√
√
√
√
√
√
√
√
Store Low Accumulator With Shift
TMS320C1x devices: Store the 16 LSBs of the accu-
mulator into the addressed data-memory location. A
shift value of 0 must be specified if the ARP is to be
changed.
TMS320C2x, TMS320C2xx, and TMS320C5x de-
vices: Store the 16 LSBs of the accumulator into the
addressed data-memory location. If a shift is specified,
shift the contents of the accumulator before storing.
Shift values are 0, 1, or 4 bits (TMS320C20) or from 0
to 7 bits (TMS320C2x/2xx/5x).
SAMM
dma
SAMM {
ind
} [
, next ARP
]
√
√
Store Accumulator in Memory-Mapped Register
Store the low word of the accumulator in the addressed
memory-mapped register. The upper 9 bits of the data
address are cleared, regardless of the current value of
DP or the 9 MSBs of AR (ARP).
SAR
AR, dma
SAR
AR,
{
ind
} [
, next ARP
]
√
√
√
√
√
√
√
√
Store Auxiliary Register
Store the contents of the specified auxiliary register in
the addressed data-memory location.
SATH
√
Barrel-Shift Accumulator as Specified
by T Register 1
If bit 4 of TREG1 is a 1, barrel-shift the accumulator
right by 16 bits; otherwise, the accumulator is unaf-
fected.
SATL
√
Barrel-Shift Low Accumulator as Specified
by T Register 1
Barrel-shift the accumulator right by the value speci-
fied in the 4 LSBs of TREG1.
SBB
√
Subtract ACCB From Accumulator
Subtract the contents of the ACCB from the accumula-
tor. The result is stored in the accumulator; the accu-
mulator buffer is not affected.