Filter
Top Products
Hardware Description
3-36 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
The clock domains for the PB926EJ-S are:
ARM926EJ-S PXP Development Chip
The ARM926EJ-S PXP Development Chip CPU clock is normally a
multiplied version of GLOBALCLK that is based on OSC0.
Alternatively, the CPU can be clocked from a 32kHz clock or OSC2 to
test low-power operating modes.
There are three external AHB bridges on the chip. These normally
operate in synchronous mode and the bridge clocks are based on the CPU
clock. (The internal AHB clock HCLK is divided down from the CPU
clock.) In asynchronous mode, the external part of the AHB bridges can
be clocked from OSC0, OSC1, OSC2, or OSC3 depending on the clock
multiplexors.
The RTC in the ARM926EJ-S PXP Development Chip is clocked from a
dedicated 32kHz signal that is derived from the 32kHz oscillator module.
The CLCDC uses OSC4 as the reference for its data clock.
The memory and MBX clocks are derived from the internal AHB clock.
The UART, SSP, and SCI peripherals located in the ARM926EJ-S PXP
Development Chip are normally clocked from the internal HCLK. An
external 24MHz clock from the programmable clock generators can be
selected as the reference clock instead of using the clock source inside the
chip.
The dual timer modules in the ARM926EJ-S PXP Development Chip are
clocked from an external 1MHz clock derived from the 24MHz
reference.
FPGA The FPGA contains clock control logic that can set the frequency of the
programmable clock generators and direct their outputs to internal and
external peripherals.
PCI A PCICLK is derived from the 33MHz or 66MHz reference oscillator on
the PCI backplane. The PCI clock is connected to the PCI controller in
the FPGA to synchronize accesses with the PCI bus. The PCI controller
is also connected to the AHB S and AHB M2 buses. The clocks for the
AHB buses come from the clock multiplexor.
Audio CODEC
The Audio CODEC has a dedicated crystal oscillator. The reference
clock from the CODEC is connected to the AACI in the FPGA.