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Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-47
Table 3-7 to Table 3-9 on page 3-48 list the source of the bridge clocks for different
values of the HCLKCTRL[7:0] signals (from SYS_CONFIGDATA1[23:16]). The
default value of HCLKCTRL[7:0] is
0xE0
.
Table 3-7 HCLKM1 selection
HCLKCTRL signal
[4] [0] [1] [5] HCLKM1 driven by:
11XX
GLOBALCLK (driven from tile,
nGLOBALCLKEN pulled HIGH)
10XX
GLOBALCLK (driven from OSC0)
0X1X
HCLKM1L2S and HCLKM1L2F (from tile)
0X01
OSC0 (default)
0X00
OSC1
Table 3-8 HCLKM2 selection
HCLKCTRL signal
[4] [0] [2] [6] HCLKM2 driven by:
11XX
GLOBALCLK (driven from tile,
nGLOBALCLKEN pulled HIGH)
10XX
GLOBALCLK (driven from OSC0)
0X1X
HCLKM2L2S and HCLKM2L2F (from tile)
0X01
OSC0 (default)
0X00
OSC2