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Hardware Description
3-16 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
3.1.5 AHB monitor
The ARM926EJ-S PXP Development Chip contains a multi-layer AHB system to
provide high bandwidth connectivity between the various bus masters and slaves both
within and outside the ARM926EJ-S PXP Development Chip.
The AHB layer monitors observe the activity on their respective bus signals to produce
real-time information that is exported off-chip to a logic analyzer.
The AHB monitor also contains event counters that monitor bus transactions. The event
counters can be accessed through the both the ARM DATA AHB and ARM AHB S
buses. The event counters provide a simple mechanism for monitoring bus utilization.
The AHB debug port consists of 33 output pins that export status data packets at the
AHB clock rate. A localized clock is exported on AHBMONITOR[33]. The interface
between the development chip and the debug connector is shown in Figure 3-7.
The base address of the AHB monitor is at
0x101D0000
.
Figure 3-7 AHB monitor connection
See the ARM926EJ-S Reference Manual and AHB monitor on page 4-41.