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4-98 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
4.25.1 PrimeCell Modifications
The PrimeCell UART varies from the industry-standard 16C550 UART device as
follows:
• receive FIFO trigger levels are 1/8, 1/4, 1/2, 3/4, and 7/8
• the internal register map address space, and the bit function of each register differ
• the deltas of the modem status signals are not available.
• 1.5 stop bits not available (1 or 2 stop bits only are supported)
• no independent receive clock.