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Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-5
The ARM926EJ-S PXP Development Chip incorporates the following features:
ARM926EJ-S
The ARM926EJ-S CPU is a member of the ARM9 Thumb
®
family. The
ARM926EJ-S (r0p3) macrocell is a 32-bit cached processor with
ARMv5TE architecture that supports the ARM and Thumb instruction
sets and includes features for direct execution of Java byte codes.
Executing Java byte codes requires the Java Technology Enabling Kit
(JTEK).
The ARM926EJ-S contains a Memory Management Unit (MMU), 32KB
data and instruction caches, and 32KB of data and instruction Tightly
Coupled Memory (TCM). The TCM operates with a single wait-state and
provides higher data rates than external memory.
ETM9 The Embedded Trace Macrocell (ETM) provides signals for off-chip
trace. The ETM transmits a 16-bit packet to an external trace port
analyzer where the signals can be stored and later analyzed to reconstruct
the code flow.
VFP9 This high-performance, low-power Vector Floating-Point (VFP)
coprocessor implements the VFPv2 vector floating-point architecture.
MOVE The MOVE coprocessor is a video encoding accelerator designed to
accelerate Motion Estimation (ME) algorithms within block-based video
encoding schemes such as MPEG4 and H.263. For more information on
the MOVE coprocessor, see the ARM MOVE Coprocessor Technical
Reference Manual.
MBX This high-performance graphic accelerator operates on 3D scene data (as
batches of triangles) sent from the main processor. Triangles are written
directly to a tile accelerator so that the CPU is not stalled during
processing. For more information on the MBX coprocessor, see the ARM
MBX HR-S Graphics Core Technical Reference Manual.
Clock control
The ARM926EJ-S PXP Development Chip contains deskew PLL that
uses an external reference clock to generate internal clocks for the CPU,
AHB bus, memory, and off-chip peripherals. Dividers in the chip are
programmable and give considerable flexibility in clock rates for the
CPU, bridges, and memory.
AHB buses The ARM926EJ-S processor uses two separate AHB masters for
instructions and data to maximize system speed. The DMA controller has
two AHB masters. The CLCD controller has one AHB master.