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RealView Logic Tile
F-6 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
Caution
The RealView Logic Tile mounted on the PB926EJ-S must use the default 3.3V signal
levels.
F.3.3 RealView Logic Tile I/O
The signals from the UART0, UART1, UART2, SSP, and SCI connectors to the
ARM926EJ-S PXP Development Chip can be isolated by pulling the nDRVINENx
signals HIGH. This enables logic in the RealView Logic Tile to safely drive the
Development Chip signals without contention with external devices on the connectors
(see Figure F-4).
Figure F-4 RealView Logic Tile tristate for I/O
nDRVINEN1
I/O connectors
UART0
UART1
SSP
SCI0
UART2
UART0
nDRVINEN0
UART1
UART2
SCI0
SSP
UART0
UART1
SSP
SCI0
UART2
Logic Tile connectors
ARM926EJ-S Dev. Chip
GPIO
GPIO
en