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xvi Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
Figure D-3 PCI backplane .......................................................................................................... D-6
Figure D-4 JTAG signal flow on the PCI backplane ................................................................... D-9
Figure D-5 AMP Mictor connector J4 ........................................................................................ D-11
Figure D-6 PCI expansion board JTAG connector J5 .............................................................. D-12
Figure E-1 Dynamic memory board block diagram .................................................................... E-2
Figure E-2 Static memory board block diagram ......................................................................... E-3
Figure E-3 Memory board installation locations ......................................................................... E-5
Figure E-4 Chip select information block .................................................................................... E-8
Figure E-5 Samtec connector ................................................................................................... E-13
Figure E-6 Dynamic memory board layout ............................................................................... E-20
Figure E-7 Static memory board layout .................................................................................... E-20
Figure F-1 Signals on the RealView Logic Tile expansion connectors ...................................... F-2
Figure F-2 RealView Logic Tile fitted on PB926EJ-S ................................................................. F-3
Figure F-3 HDRX, HDRY, and HDRZ (upper) pin numbering .................................................... F-5
Figure F-4 RealView Logic Tile tristate for I/O ........................................................................... F-6
Figure F-5 Clock signals and the RealView Logic Tile ............................................................. F-10
Figure F-6 Bus signals for RealView Logic Tile and FPGA ...................................................... F-13
Figure G-1 Nodes added to Connection Control window ............................................................ G-5
Figure G-2 The Connection Control window ............................................................................... G-6
Figure G-3 ARM926EJ-S PXP Development Chip detected ...................................................... G-7
Figure G-4 Error shown when unpowered devices are detected ................................................ G-7
Figure G-5 Error shown when no devices are detected .............................................................. G-8
Figure G-6 Error shown when the USB debug port is not functioning ........................................ G-8
Figure G-7 Connection Properties window ................................................................................. G-8
Figure G-8 The Debug tab of the Register pane ....................................................................... G-10