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Programmer’s Reference
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 4-83
Limitations of the PCI interface
The following limitations apply to the PCI interface present on the PB926EJ-S:
• The interface is 32-bit only.
• 0-bit, 24-bit and unaligned 16-bit transfers are not supported.
• The initiator creates only single reads and writes. This is quite inefficient and
results in low performance. It does, however, simplify the logic in the FPGA and
allows 66MHz performance.
• The target issues a retry response for reads until the data is ready.
• The target issues a retry response for reads or writes when the fifo is full (target
has a 512 deep FIFO, initiator fifo is 16 deep)
• If another master accesses the PB926EJ-S and it responds with 'retry' or
'disconnect without data', then this access must repeated before any other master
accesses to the PB926EJ-S.
• The PB926EJ-S breaks up burst transfers. It typically completes the first cycle
and then responds with 'disconnect without data'. The initiator must then retry
with the address that responded with the disconnect.
• Only three out of five configuration base registers are usable.
• Cardbus CIS Pointer and Expansion ROM configuration registers are not
implemented.
• There is no support for BIST.
• The target will only respond to some of sixteen PCI bus commands, and initiator
only creates six of the cycle types (see Table 4-58 on page 4-84).