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Hardware Description
3-70 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
The controller uses a local VL-Bus host interface with a bridge to the AHB bus provided
by the FPGA. The FPGA generates the appropriate access control signals for the host
side of the Ethernet controller. The VL-Bus is a synchronous bus that supports 32-bit
accesses.
The LAN91C111 is a little-endian device. The default configuration for the system bus
is also little-endian. If you configure the system bus for big-endian operation you must
perform half-word and byte swapping in software.
A serial EEPROM provides the following parameters to the LAN91C111 at reset:
• the individual MAC address, that is, the Ethernet MAC address
• Media Independent Interface (MII) interface configuration
• register base address.
When the PB926EJ-S is manufactured, an ARM value for the Ethernet MAC address
and the register base address are loaded into the EEPROM. The register base address is
0. A unique MAC address is programmed at manufacture, but the address can be
reprogrammed if required. Reprogramming of the EEPROM is done through Bank 1
(general and control registers).