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Hardware Description
3-50 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
where:
VDW Is the VCO divider word (4 – 511) from SYS_OSCx[8:0]
RDW Is the reference divider word (1 – 127) from SYS_OSCx[15:9]
DIVIDE Is the divide ratio (2 to 10) selected from SYS_OSCx[18:16]:
•
b000
selects divide by 10
•
b001
selects divide by 2
•
b010
selects divide by 8
•
b011
selects divide by 4
•
b100
selects divide by 5
•
b101
selects divide by 7
•
b110
selects divide by 3
•
b111
selects divide by 6.
For more information on the ICS clock generator and a frequency calculator, see the ICS
web site at
www.icst.com
. For details of the clock control registers, see Status and system
control registers on page 4-17.
Selecting slow start
The PB926EJ-S can be restarted with low-frequency clocks. This is useful, for example,
if you are testing a peripheral in an external RealView Logic Tile that cannot support
high frequency operation at startup. This mode does not require you to write a
startup-application that writes to SYS_OSC0.
To restart the system in low-frequency mode, set switch S1-5 to ON and power-cycle
the system or press the DEV CHIP CONFIG pushbutton. The resulting frequencies are:
OSCCLK0 The reference clock is programmed for 10MHz operation. The ratios for
the clock dividers are not changed.
HCLKEXT This 10MHz clock controls the external half of the AHB bridges when
they are operating in synchronous mode.
HCLK This 20MHz clock controls the internal half of the AHB bridges and is
the reference clock for the memory controllers.
CPUCLK This 60MHz clock drives the ARM926EJ-S processor.
To return to the default operating mode, set switch S1-5 to OFF and reset the system.
Selecting the low-frequency clocks in power-saving mode
The system controller in the ARM926EJ-S PXP Development Chip can switch the
system into power-saving modes (slow, doze, and sleep).