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Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-59
3.7 Character LCD controller
The FPGA contains a simple controller that provides an interface to a standard
HD44780 16 x 2 character LCD alphanumeric display module.
The character display has an 8-bit interface, DB[7:0] (CHARLCDD[7:] from the
controller).
The device is controlled by the E, RnW, and RS pins. The controller drives these pins
with the CHARLCDE, CHARLCDnWRITE, and CHARLCDRS signals.
A 3.3V to 5V translation buffer is used to interface the to the 5Vlogic levels of the
character LCD. RS selects the access of either the data register or the command register.
A read of the command register returns the busy flag in DB[7].
LK10 is installed at the factory to match the voltage requirement of the particular
display module installed on the board.
Note
The LCD display is much slower than the peripheral bus. Poll the busy flag or write an
interrupt service routine to determine if the device is ready to accept commands. See
Character LCD display on page 4-44.
An interrupt signal is generated by the character LCD controller a short time after the
raw data is valid. However this interrupt signal is reserved for future use and you must
use a polling routine instead of an interrupt service routine.