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4-100 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
4.27 Vector Floating Point, VFP9
The VFP9-S coprocessor is an implementation of the Vector Floating-point
Architecture version 2 (VFPv2). It provides low-cost floating-point computation that is
fully compliant with the ANSI/IEEE Std. 754-1985, IEEE Standard for Binary
Floating-Point Arithmetic. The VFP9-S coprocessor supports all addressing modes
described in section 5 of the ARM Architecture Reference Manual.
Note
The following operations from the IEEE 754 standard are not supplied by the VFP9-S
instruction set:
• remainder
• round floating-point number to integer-valued floating-point number
• binary-to-decimal conversions
• decimal-to-binary conversions
• direct comparison of single-precision and double-precision values.
Complete implementation of the IEEE 754 standard is achieved by support code that is
provided with the ARM compilation tools.
The latest VFP support code can be obtained as part of Application Note 98. If you are
using RealView Compilation Tools (RVCT), the appropriate code and documentation
are provided within your installation. If you are using the ARM Developer Suite (ADS)
1.2, Application Note 98 can be downloaded from
www.arm.com/support/
.
Table 4-77 VFP9 implementation
Property Value
Location ARM926EJ-S PXP Development Chip
Memory base address The VFP registers are not memory-mapped. Access is from the
coprocessor instructions.
Interrupt NA
DMA NA
Release version VFP9 r0p1
Reference documentation ARM VFP9 Coprocessor Technical Reference Manual