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Hardware Description
3-8 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
Configuration switches
The S1 boot option select switches are listed in Table 3-1. For more information on
setting boot memory options, see Setting the configuration switches on page 2-3 and
Configuration and initialization on page 4-9, and Boot Select Register, SYS_BOOTCS
on page 4-34. Switch S1 values determine the BOOTCSSEL[7:0] signals. (S1-1
controls BOOTCSSEL0 and S1-8 controls BOOTCSSEL7.)
Table 3-1 Configuration switch S1
Switch Description
S1-1
and
S1-2
Controls the chip select signals for the static memory, see also Setting the configuration switches
on page 2-3.
The factory default setting is booting from Disk-on-Chip NAND flash, S1-1 OFF and S1-2 OFF.
S1-3 Forces asynchronous AHB bridge mode.
The factory default is OFF, the mode for each bridge is selected by the value of bits [24:22] of the
SYS_CFGDATA2 register. The default for the register bits is LOW, synchronous mode used for
all bridges, see Configuration registers SYS_CFGDATAx on page 4-25.
S1-4 Reserved for selection of the controller to use for static memory.
The factory default is OFF.
Caution
This switch must not be changed from the default position as the functionality is not supported.
S1-5 Selects low-frequency startup mode. OSCCLK0 is programmed for 10MHz.
This startup mode is used, for example, when there is an external Logic Tile connected that cannot
support high frequency at startup.
The factory default is OFF.
See Selecting slow start on page 3-50.
S1-6
and
S1-7
Selects one of four PB926EJ-S FPGA images to load on power up (or after the FPGA CONFIG
button is pressed).
The factory default is FPGA image zero, S1-7 OFF and S1-6 OFF.
Note
Only one image is supplied with the PB926EJ-S. See FPGA configuration on page 3-18.
S1-8 Logic Tile stack image. Selects one of two Logic Tile FPGA images to load on power up.
The factory default is Logic Tile FPGA image zero, S1-8 OFF. See the documentation provided
with your Logic Tile for details on the FPGA_IMAGE signal.