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Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-69
3.10.1 About the SMSC LAN91C111
The SMCS LAN91C11 is a fast Ethernet controller that incorporates a Media ACcess
(MAC) Layer, a PHYsical (PHY) layer, and an 8KB dynamically configurable transmit
and receive FIFO.
The controller supports dual-speed 100Mbps or 10Mbps and auto configuration. When
auto configuration is enabled, the chip is automatically configured for network speed
and for full or half-duplex operation.
TPI+, TPI- Signal from interface to controller
LEDA, LEDB Activity indicator LEDs. The function of the LEDs can be configured by writing
to a LAN91C111 register.
ETHRESET Reset signal to LAN91C111
ETHARDY Asynchronous ready signal
ETHSRDY Synchronous ready signal
ETHnRDYRTN Signals to the controller to complete synchronous read cycles
ETHnADS Latches address to controller
ETHLCLK Clock to controller interface
ETHnRD Read signal for asynchronous interface
ETHnWR Write signal for asynchronous interface
ETHnDATACS Enables accesses to the controller data path
ETHnCYCLE Used to control EISA burst mode synchronous cycles if LOW
ETHAEN Address valid signal to controller.
ETHnLDEV Asserted LOW if the address enable signal, ETHAEN, is low and the address lines
decode to the controller address programmed into the base address register
ETHWnR Defines bus direction for synchronous accesses
ETHnVLBUS This signal is connected to ground by a pull-down resistor. If LOW, the controller
uses VL bus accesses. If HIGH, the controller uses EISA DMA accesses.
Table 3-16 Ethernet signals (continued)
Signal Description