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xiv Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
Figure 3-13 Programmable reset level ....................................................................................... 3-26
Figure 3-14 Boot memory remap logic ....................................................................................... 3-28
Figure 3-15 Power-on reset and configuration timing ................................................................ 3-32
Figure 3-16 Standby switch and power-supply control .............................................................. 3-34
Figure 3-17 Clock architecture ................................................................................................... 3-35
Figure 3-18 ARM926EJ-S PXP Development Chip internal multiplexors .................................. 3-39
Figure 3-19 Default clock sources and frequencies ................................................................... 3-42
Figure 3-20 Clock sources for asynchronous AHB bridges ....................................................... 3-45
Figure 3-21 Serial data and SYS_OSCx register format ............................................................ 3-49
Figure 3-22 Example of selecting a tile clock for the AHB S bridge ........................................... 3-53
Figure 3-23 Clock multiplexors ................................................................................................... 3-55
Figure 3-24 Audio interface ........................................................................................................ 3-57
Figure 3-25 Character display .................................................................................................... 3-60
Figure 3-26 Display interface ..................................................................................................... 3-62
Figure 3-27 DMA channels ........................................................................................................ 3-66
Figure 3-28 Ethernet interface architecture ................................................................................ 3-68
Figure 3-29 GPIO block diagram ............................................................................................... 3-71
Figure 3-30 External and internal interrupt sources ................................................................... 3-72
Figure 3-31 KMI block diagram .................................................................................................. 3-74
Figure 3-32 MMI interface .......................................................................................................... 3-77
Figure 3-33 PCI bridge ............................................................................................................... 3-79
Figure 3-34 Serial bus block diagram ........................................................................................ 3-80
Figure 3-35 SCI block diagram .................................................................................................. 3-82
Figure 3-36 SSP block diagram ................................................................................................. 3-84
Figure 3-37 Switch and LED interface ....................................................................................... 3-87
Figure 3-38 UARTs block diagram ............................................................................................. 3-89
Figure 3-39 UART0 interface ..................................................................................................... 3-89
Figure 3-40 Simplified interface for UART[3:1] .......................................................................... 3-90
Figure 3-41 OTG243 block diagram ........................................................................................... 3-92
Figure 3-42 Test and debug connectors, links, and LEDs ......................................................... 3-95
Figure 3-43 JTAG connector signals ........................................................................................ 3-101
Figure 3-44 JTAG signal routing .............................................................................................. 3-102
Figure 3-45 RealView Logic Tile JTAG circuitry ....................................................................... 3-103
Figure 4-1 ARM Data bus memory map .................................................................................... 4-8
Figure 4-2 Booting from Disk on Chip ..................................................................................... 4-12
Figure 4-3 Booting from NOR flash .......................................................................................... 4-13
Figure 4-4 Booting from static expansion memory ................................................................... 4-14
Figure 4-5 Booting from AHB expansion .................................................................................. 4-15
Figure 4-6 ID Register, SYS_ID ............................................................................................... 4-21
Figure 4-7 SYS_SW ................................................................................................................. 4-21
Figure 4-8 SYS_LED ................................................................................................................ 4-22
Figure 4-9 Oscillator Register, SYS_OSCx .............................................................................. 4-23
Figure 4-10 Lock Register, SYS_LOCK ..................................................................................... 4-24
Figure 4-11 SYS_CFGDATA1 ................................................................................................... 4-25
Figure 4-12 SYS_CFGDATA2 ................................................................................................... 4-26
Figure 4-13 SYS_RESETCTL .................................................................................................... 4-3
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Figure 4-14 SYS_MCI ................................................................................................................ 4-32