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ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 4-93
Table 4-68 Register values for Intel flash, async page mode
Address
Name of SSMC
register
Value Description
+0xE0 SMBIDCYR7
0x0
Idle Cycle Control Register for bank 1
+0xE4 SMBWSTRDR7
0x4
Read Wait State Control Reg bank 1
+0xE8 SMBWSTWRR7
0x3
Write Wait State Control Reg Bank 1
+0xEc SMBWSTOENR7
0x0
Output Enable Assertion Delay 1
+0xF0 SMBWSTWENR7
0x1
Write Enable Assertion Delay 1
+0xF4 SMBCR7
0x303521
Control Register for memory bank 1
+0xFC SMBWSTBRDR7
0x0
Burst Read Wait state Control Reg 1
Table 4-69 Register values for Samsung SRAM
Address
Name of SSMC
register
Value Description
+0x40 SMBIDCYR2
0x0
Idle Cycle Control Register for bank 2
+0x44 SMBWSTRDR2
0x2
Read Wait State Control Reg bank 2
+0x48 SMBWSTWRR2
0x2
Write Wait State Control Reg Bank 2
+0x4c SMBWSTOENR2
0x0
Output Enable Assertion Delay 2
+0x50 SMBWSTWENR2
0x1
Write Enable Assertion Delay 2
+0x54 SMBCR2
0x303021
Control Register for memory bank 2
+0x5c SMBWSTBRDR2
0x0
Burst Read Wait state Control Reg 2
Table 4-70 Register values for Spansion BDS640
Address
Name of SSMC
register
Value Description
+0x60 SMBIDCYR3
0x0
Idle Cycle Control Register for bank 3
+0x64 SMBWSTRDR3
0x3
Read Wait State Control Reg bank 3
+0x68 SMBWSTWRR3
0x2
Write Wait State Control Reg Bank 3