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B-8 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
Table B-7 Peripherals and controller timing
Peripheral signals Clock tov toh tis tih
CLCDC outputs (CLD[23:0], CLPOWER, CLLP, CLCP,
CLFP, CLAC, and CLLE)
The maximum frequency of CLCDCLK is 100MHz for a
t
cyc
of
10ns.
CLCDCLK 12.5ns -2.5ns - -
SCI outputs (nSCICLKOUTEN, SCICLKOUT,
nSCIDATAOUTEN, nSCICLKEN, and nSCIDATAEN)
SCIREFCLK 14ns -1ns - -
SCI inputs (SCICLKIN, SCIDATAIN, and SCIDETECT)
The maximum frequency of SCIREFCLK is 100MHz for a
t
cyc
of 10ns.
SCIREFCLK - - 12ns -14ns
SSP outputs (SSPFRMOUT, SSPCLKOUT, SSPTXD,
nSSPCTLOE, and nSSPOE)
SSPCLK 4ns -2ns - -
SSP inputs (SSPRXD, SSPFRMIN, and SSPCLKIN)
The maximum frequency of SSPCLK is 100MHz for a
t
cyc
of
10ns.
SSPCLK - - 12ns -14ns