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Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-73
The primary interrupt controller manages interrupts from internal devices and provides
11 pins for use by the external secondary interrupt controller and multiplexor present in
the FPGA. VICINTSOURCE31 is the output from the secondary controller.
VICINTSOURCE[30:21] can be driven from individual interrupt signals from
peripherals in the FPGA or on a RealView Logic Tile.
For details on the programming model for the interrupt controllers, see:
• the ARM926EJ-S Development Chip Reference manual
• the ARM PrimeCell Vector Interrupt Controller (PL190) Technical Reference
Manual manual
• Primary interrupt controller on page 4-58.