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RealView Logic Tile
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. F-11
F.3.5 AHB buses used by the FPGA and RealView Logic Tiles
AHB M1, AHB M2, and AHB S buses are connected to both the FPGA and to the
RealView Logic Tile stack. However, the user-implemented system in the tile must
co-operate with the system implemented within the PB926EJ-S FPGA when using
these buses:
AHB M1 The AHB M1 bus can only be connected to AHB slaves in the Logic Tile
stack.
AHB M2 The AHB M2 bus can only be connected to AHB slaves in the Logic Tile
stack.
AHB S The AHB S bus can only be connected to AHB masters in the Logic Tile
stack. The Logic Tile AHB master can access an AHB M1 or AHB M2
slave in a logic tile by passing the access through the bus matrix in the
development chip.
AHB M1
The PB926EJ-S FPGA does not contain any slaves attached to the AHB M1 bus. The
ARM926EJ-S PXP Development Chip memory map assigns the top 2GB of address
space (
0x80000000
–
0xFFFFFFFF
) to this bus, so a RealView Logic Tile can contain
user-supplied slaves that occupy any of this space. The RealView Logic Tile FPGA
must give a response to all transfers that are generated on the AHB M1 bus, even those
to addresses in the range
0x00000000
–
0x7FFFFFFF
. The PB926EJ-S never generates these
addresses on the AHB M1 bus. A separate tile master might, however, generate accesses
to this region.
It is normal to direct any unwanted transfers to a "default" slave that issues an AHB
ERROR response to any active transfers, but a simple zero wait-state OKAY response
would be sufficient to ensure that a system functions correctly. (This is analogous to an
Integrator Logic Module being responsible for all of the 256MB allocated to the Logic
Module, even if the user-supplied peripherals occupy only a small address space).
If there is not a RealView Logic Tile fitted, pull-up and pull-down resistors on the
PB926EJ-S ensure that all AHB M1 transfers receive a zero-wait state OK response.
AHB M2
Transactions in the addresses range
0x14000000
–
0x1FFFFFFF
are directed to AHB M2 by
the ARM926EJ-S PXP Development Chip, but do not select any of the slaves within the
PB926EJ-S FPGA.
These addresses can be used for expansion slaves within a RealView Logic Tile. If a
RealView Logic Tile contains multiple expansion AHB slaves on AHB M2 then it must
also include a multiplexor to combine these slave outputs. The final stage of