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Index-2 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
Logic Analyzer 3-104
CLCD
adaptor connectors C-15
controller 3-61, 4-47
register 4-32, 4-34
Clocks
architecture 3-35
changing 3-43
development chip 3-39
logic tile 3-52
multiplexor 3-54
peripheral 3-51, 3-54
programmable 3-48
RealView Logic Tile F-7
reset register 4-39
restrictions B-5
test register 4-40
Configuration
boot memory 2-3
Boot Monitor 2-7
FPGA 3-18
interfaces 3-94
JTAG 2-8
logic 3-22
memory 4-9
memory board E-3
PCI 4-79
RECONFIG 3-9
registers 4-17, 4-25
reset 3-22, 3-32
runtime 3-10
switches 2-3, 3-7
touchscreen C-13
Trace port 2-10
Configure
Boot Monitor commands 2-16
boot select 4-34
CLCD display C-6
PCI D-2
RealView ICE G-1
Smart Card 3-82
USB debug G-1
utility 2-23
Conventions
numerical xxi
signal naming xxi
timing diagram xx
typographical xix
D
DMA
mapping registers 4-52
registers 4-37
E
Electrical
specification B-2
Embedded Logic Analyzer A-38
Ethernet
controller 3-69
interface 3-68, 4-55
F
FPGA
architecture 3-17
configuration 3-18
debug signals A-40
reload sequence 3-20
G
GPIO
interface 4-56
signals 3-71
I
Interrupt
controllers 4-57
handling 4-63
secondary 4-61
sources 3-72
J
JTAG
configuration 2-8
signals 3-98, A-36, D-9
support 3-96
USB debug 2-8
K
KMI
interface 3-74, 4-67
L
LAN91C111 3-69
LCD
adaptor board C-2
character display 4-44
display resolution 4-49
LED
user 3-87
Library
platform 2-25
M
MBX
interface 4-68
MCI
interface 3-75, 4-70
register 4-31
Mechanical
CLCD adaptor C-19
memory board E-20
PCI backplane D-6
VPB//PB926EJ-S B-9
Memory
aliasing at reset 3-27
boot 2-3
card 3-76
characteristics 4-15
connector E-13
expansion 4-13
expansion board E-2
flash commands 2-17
flash register 4-32
interface 3-15
map 4-3
MPMC 4-71
NOR flash 4-12
PCI 4-76
remapping 4-9
SDRAM 4-10
SSMC 4-91