ARM ARM DUI 0224I Computer Hardware User Manual


 
Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-29
3.3.4 Reset signals
Table 3-4 describes reset signals.
Table 3-4 Reset signal descriptions
Name Function
AACIRESET System reset to audio CODEC.
APPLYCFGWORD This internal signal causes the FPGA to apply configuration data from the
SYS_CFGDATAx registers in the FPGA to the M1 and M2 data buses, see
Configuration registers SYS_CFGDATAx on page 4-25.
nBOARDPOR This signal resets the configuration PLD and configuration flash.
This signal is also used to generate the nTRST pulse at power on.
nCONFIGCLR Loads the default configuration for the ARM926EJ-S PXP Development Chip. The
default configuration data is hard-coded into the ARM926EJ-S PXP Development
Chip.
CONFIGINIT This signal causes the ARM926EJ-S PXP Development Chip to load configuration
data from the M1 and M2 data buses. This enables configuration of the chip without
resetting the entire system.
C_nSRST JTAG open-collector reset signal (shared with FPGAnINIT) to or from the Logic
Tile. This signal is part of the configuration JTAG chain.
C_nTRST JTAG TRST signal to the configuration JTAG chain in the Logic Tile. This signal is
part of the configuration JTAG chain.
nDOCBUSY Memory status signal from the Disk-on-Chip. The DoC requires approximately 27ms
after reset is applied in order to initialize its internal controllers.
nDOCRESET System reset to Disk-on-Chip memory.
D_nSRST JTAG open-collector reset request signal to or from the Logic Tile. This signal is part
of the debug JTAG chain.
D_nTRST JTAG TRST signal to the debug JTAG chain in the Logic Tile. This signal is part of
the debug JTAG chain.
ETHnRESET System reset to Ethernet controller.
FPGA_nPROG The FPGA_nPROG signal forces all FPGAs in the system to reconfigure. This signal
enables the FPGAs to be reconfigured without powering-down the system.
GLOBAL_DONE This is an open-collector configuration signal that goes HIGH when all FPGAs have
finished configuring. The system is held in reset until this signal goes HIGH.