Filter
Top Products
Programmer’s Reference
4-74 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
4.17 PCI controller
The PCI controller is implemented in the FPGA and controls the interface to the PCI
bus.
Caution
The PCI controller is provided by Xilinx. The source HDL for this device is not
provided on the CD. The PCI controller will be deleted if you rebuild the FPGA image.
The PCI slave bridge connected to AHB M2 recognizes addresses
0x41000000
to
0x6FFFFFFF
as being intended for a target within the PCI address space of the memory
map, and passes accesses within this region to the PCI bus. The PCI master bridge
connected to the PCI bus passes accesses to the AHB S bus.
Table 4-48 PCI controller implementation
Property Value
Location FPGA
Memory base address
0x10001000
for the map and control registers
PCI configuration region is
0x41000000–0x42FFFFFF
PCI I/O is
0x43000000-0x43FFFFFF
PCI memory region 0 is
0x44FFFFFF-0x4FFFFFFF
PCI memory region 1 is
0x5000000-0x5FFFFFFF
PCI memory region 2 is
0x6000000-0x6FFFFFFF
Interrupt PCI0 to 27 on primary and secondary controllers PCI1 to 28 on
primary and secondary controllers PCI2 to 29 on primary and
secondary controllers PCI3 to 30 on primary and secondary
controllers.
DMA None. Memory to memory transfers can be set up in the
DMAC.
Release version Custom logic (Xilinx)
Reference documentation PCI v2.2 Specification (see the PCI SIG web site at
www.pcisig.com
) See also Table 4-50 on page 4-75, PCI
interface on page 3-79, and Appendix D PCI Backplane and
Enclosure)