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RealView Logic Tile
F-12 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
multiplexing to combine with the PB926EJ-S slave outputs must be done with tristates
in the RealView Logic Tile FPGA and PB926EJ-S FPGA. (This combination of
multiplexing and tristates is identical to that used in Integrator Modules).
It is recommended to use AHB M1 (not AHB M2) for expansion slaves in a RealView
Logic Tile. The large address space will permit simpler decoding which will allow the
bus to run faster. Avoiding the AHB M2 bus will make development simpler because
design errors will not stop the PB926EJ-S peripherals from working. The RealView
Logic Tile FPGA must respond to all transfers in the range
0x14000000
–
0x1F000000
.
These addresses could be directed to a default slave as described in AHB M1 on
page F-11 or to a simple zero-wait state OKAY response. The HRESP and HREADY
outputs must be tristated if other addresses are selected.
If there is not a RealView Logic Tile fitted, a default slave in the PB926EJ-S FPGA is
enabled and accesses to this range receive a simple zero-wait state OKAY response to
BUSY and IDLE requests. An ABORT response is returned for active transfers.
AHB S
The PCI bridge in PB926EJ-S FPGA contains an AHB master that can drive the AHB
S port of the ARM926EJ-S PXP Development Chip. If a RealView Logic Tile
implements another expansion master then it also must add an arbiter for this AHB. This
arbiter takes HBUSREQ from the PCI master in the FPGA and drives HGRANT back
to that master. If the RealView Logic Tile does not contain any expansion AHB masters
then it should drive HGRANT permanently to 1. There is a pullup resistor that does this
when no LT is present.
If a RealView Logic Tile contains multiple expansion AHB masters then it must also
include a multiplexor to combine these master outputs. The final stage of multiplexing
to combine with the PCI master outputs must be done with tristates in the RealView
Logic Tile FPGA and RealView FPGAs (This combination of muxing and tristates is
identical to that used in Integrator Modules).
A RealView Logic Tile that implements an master on the AHB S bus can also access an
AHB M1 or AHB M2 slave implemented in the same RealView Logic Tile or in a
different RealView Logic Tile in the tile stack. After the RealView Logic Tile is granted
control of the S bus, requests to the slave buses on the tiles are decoded by the bus matrix
in the development chip.
Example RealView Logic Tile implementation
Figure F-6 on page F-13 shows a RealView Logic Tile that has a single master and
several slaves.