Filter
Top Products
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. xiii
List of Figures
RealView Platform Baseboard for ARM926EJ-S
User Guide
Key to timing diagram conventions ............................................................................. xx
Figure 1-1 PB926EJ-S layout ..................................................................................................... 1-3
Figure 1-2 PB926EJ-S block diagram ........................................................................................ 1-6
Figure 2-1 Location of S1-1 and S6-1 ........................................................................................ 2-3
Figure 2-2 JTAG connection ....................................................................................................... 2-8
Figure 2-3 USB debug port connection ...................................................................................... 2-9
Figure 2-4 Example of MultiTrace and JTAG connection ......................................................... 2-10
Figure 2-5 Example of RealView ICE and RealView Trace ...................................................... 2-11
Figure 2-6 Power connectors ................................................................................................... 2-13
Figure 3-1 ARM926EJ-S PXP Development Chip block diagram .............................................. 3-4
Figure 3-2 Configuration signals from SYS_CFGDATAx ........................................................... 3-9
Figure 3-3 Example of multiple masters ................................................................................... 3-12
Figure 3-4 AHB map ................................................................................................................. 3-13
Figure 3-5 Core APB and DMA APB map ................................................................................ 3-14
Figure 3-6 Memory devices ...................................................................................................... 3-15
Figure 3-7 AHB monitor connection ......................................................................................... 3-16
Figure 3-8 FPGA block diagram ............................................................................................... 3-17
Figure 3-9 FPGA configuration ................................................................................................. 3-19
Figure 3-10 FPGA reload sequence ........................................................................................... 3-20
Figure 3-11 PB926EJ-S reset logic ............................................................................................ 3-23
Figure 3-12 Reset signal sequence ............................................................................................ 3-25