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Hardware Description
3-88 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
3.20 UART interface
Three UARTs (SER0, SER1, and SER2) are provided by the ARM926EJ-S PXP
Development Chip.
A fourth serial interface, SER3, is implemented with a PrimeCell UART incorporated
into the system controller FPGA.
The three UARTs provided by the ARM926EJ-S PXP Development Chip have the
following features:
• functionally similar to standard 16C550 devices
• port function corresponds to the DTE configuration
• SER0 (UART0) has full CTS, RTS, DCD, DSR, DTR, and RI modem control
signals
• SER1 and SER2 (UART1 and UART2) have simple modem control signals CTS
and RTS
• programmable baud rates of up to 1.5Mbits per second (the line drivers however,
are only guaranteed to 250kbps)
• 16-byte transmit FIFO
• 16-byte receive FIFO
• programmable interrupt.
Signals from UART0, UART1, and UART2 are also connected to the expansion
connector for the optional RealView Logic Tile. UART0 has two IrDA signals that are
connected to the RealView Logic Tile expansion headers: SIROUT0 and SIRIN0. There
is no IrDA interface logic on the PB926EJ-S itself.