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3-32 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
3.3.5 Reset timing
Figure 3-15 shows the power-on reset sequence.
nBOARDPOR is generated at power-up and distributed to the memory expansion
boards and to the FPGA configuration PLD. It also causes the assertion of the nTRST
signal guarantee the embedded ICE macrocell is reset in the ARM926EJ-S PXP
Development Chip.
Figure 3-15 Power-on reset and configuration timing
Note
The release time for GLOBAL_DONE depends on any Logic Tiles in the system. It
might be held LOW longer if the tiles take longer to configure.