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E-18 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
63 DATA[31] 64 SBSDA, E2PROM serial interface
data (3.3V signal level)
65 ADDR[0] 66 nRESET
67 ADDR[1] 68 nBOARDPOR, asserted on
hardware power cycle
69 ADDR[2] 70 nFLWP, flash write protect. Drive
HIGH to write to flash.
71 ADDR[3] 72 nEARLYRESET, Reset signal.
Differs from nRESET in that it is
not delayed by nWAIT.
73 ADDR[4] 74 nWAIT, Wait mode input from
external memory controller. Pull
HIGH if not used.
75 ADDR[5] 76 nBURSTWAIT, Synchronous
burst wait input. This is used by the
external device to delay a
synchronous burst transfer if LOW.
Pull to HIGH if not used.
77 ADDR[6] 78 CANCELWAIT, If HIGH, this
signal enables the system to recover
from an externally waited transfer
that has taken longer than expected
to finish. Pull LOW if not used.
79 ADDR[7] 80 nCS[4]
81 ADDR[8] 82 nCS[3]
83 ADDR[9] 84 nCS[2]
85 ADDR[10] 86 nCS[1]
87 ADDR[11] 88 Reserved, do not drive
89 ADDR[12] 90 Reserved, do not drive
91 ADDR[13] 92 Reserved, do not drive
93 ADDR[14] 94 Reserved, do not drive
Table E-6 Static memory connector signals (continued)
Pin No. Signal Pin No. Signal