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Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-99
RTCK Return TCK
(to JTAG equipment)
Some devices sample TCK and delay the time at which a
component actually captures data. Using a mechanism called
adaptive clocking, the RTCK signal is returned by the core to the
JTAG equipment, and the TCK is not advanced until the core has
captured the data. In adaptive clocking mode, RealView ICE or
Multi-ICE waits for an edge on RTCK before changing TCK. In a
multiple device JTAG chain, the RTCK output from a component
connects to the TCK input of the next device in the chain.
nCFGEN Configuration enable nCFGEN is an active LOW signal used to put the boards into
configuration mode. In configuration mode all FPGAs and PLDs
are connected to the scan chain so that they can be configured by the
JTAG equipment. (The TAP controller in the PB926EJ-S is not
accessible.)
nSRST System reset
(bidirectional)
nSRST is an active LOW open-collector signal that can be driven
by the JTAG equipment to reset the target board. Some JTAG
equipment senses this line to determine when a board has been reset
by the user.
This is also used in configuration mode to control the initialization
pin (nINIT) on the FPGAs.
Though not a JTAG signal, nSRST is described because it can be
controlled by JTAG equipment.
nTRST Test reset (from JTAG
equipment)
This active LOW open-collector signal is used to reset the JTAG
port and the associated debug circuitry on the ARM926EJ-S PXP
Development Chip. It is asserted at power-up, and can be driven by
the JTAG equipment. This signal is also used in configuration mode
to control the programming pin, nPROG, on FPGAs.
DBGRQ Debug request
(from JTAG equipment)
DBGRQ is a request for the processor core to enter the debug state.
It is provided for compatibility with third-party JTAG equipment.
Table 3-25 JTAG related signals (continued)
Name Description Function