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ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 4-101
4.28 Watchdog
The PrimeCell Watchdog module is an AMBA compliant SoC peripheral developed,
tested and licensed by ARM Limited. The Watchdog module consists of a 32-bit down
counter with a programmable timeout interval that has the capability to generate an
interrupt and a reset signal on timing out. It is intended to be used to apply a reset to a
system in the event of a software failure.
Note
The Watchdog counter is disabled if the core is in debug state.
The following Watchdog module parameters are programmable:
• interrupt generation enable/disable
• interrupt masking
• reset signal generation enable/disable
• interrupt interval.
Table 4-78 Watchdog implementation
Property Value
Location ARM926EJ-S PXP Development Chip
Memory base address
0x101E1000
Interrupt 0 on primary controller
DMA NA
Release version ARM WDOG SP805 r1p0-02ltd0
Reference documentation ARM PrimeCell Watchdog Controller (SP805) Technical
Reference Manual