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Programmer’s Reference
4-50 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
23 B7 (msb) pixel1 G3 pixel1 G2 pixel1 G2
22 B6 pixel1 G2 pixel1 G1 pixel1 G1
21 B5 pixel1 G1 (lsb) pixel1 G0 (lsb) pixel1 G0 (lsb)
20 B4 pixel1 R5 (msb) pixel1 R5 (msb) pixel1 B5 (msb)
19 B3 pixel1 R4 pixel1 R4 pixel1 B4
18 B2 pixel1 R3 pixel1 R3 pixel1 B3
17 B1 pixel1 R2 pixel1 R2 pixel1 B2
16 B0 (lsb) pixel1 R1 (lsb) pixel1 R1 (lsb) pixel1 B1 (lsb)
15 G7 (msb) pixel0 I (intensity) pixel0 B5 (msb) pixel0 R5 (msb)
14 G6 pixel0 B5 (msb) pixel0 B4 pixel0 R4
13 G5 pixel0 B4 pixel0 B3 pixel0 R3
12 G4 pixel0 B3 pixel0 B2 pixel0 R2
11 G3 pixel0 B2 pixel0 B1 (lsb) pixel0 R1 (lsb)
10 G2 pixel0 B1 (lsb) pixel0 G5 (msb) pixel0 G5 (msb)
9 G1 pixel0 G5 (msb) pixel0 G4 pixel0 G4
8 G0 (lsb) pixel0 G4 pixel0 G3 pixel0 G3
7 R7 (msb) pixel0 G3 pixel0 G2 pixel0 G2
6 R6 pixel0 G2 pixel0 G1 pixel0 G1
5 R5 pixel0 G1 (lsb) pixel0 G0 (lsb) pixel0 G0 (lsb)
4 R4 pixel0 R5 (msb) pixel0 R5 (msb) pixel0 B5 (msb)
3 R3 pixel0 R4 pixel0 R4 pixel0 B4
2 R2 pixel0 R3 pixel0 R3 pixel0 B3
1 R1 pixel0 R2 pixel0 R2 pixel0 B2
0 R0 (lsb) pixel0 R1 (lsb) pixel0 R1 (lsb) pixel0 B1 (lsb)
Table 4-30 Assignment of display memory to R[7:0], G[7:0], and B[7:0] (continued)
Memory
bit
8/8/8 1/5/5/5 5/6/5 red (lsb) 5/6/5 blue (lsb)