Filter
Top Products
Specifications
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. B-5
B.2 Clock rate restrictions
The default clock rates for reliable operation are:
CPUCLK 210MHz
MPMCCLK 70MHz
HCLK 70MHz
HCLKEXT 35MHz
MBXCLK 70MHz
SMCLK 50MHz
If you have added one or more RealView Logic Tiles, you might need to reduce these
clock rates.
For timing on the buses and peripherals, see:
• AHB bus timing on page B-6
• Memory timing on page B-7
• Peripheral timing on page B-7.
Caution
The ICS307 programmable oscillators OSC0, OSC1, OSC2, OSC3, and OSC4 can be
programmed to deliver very high clock signals (200MHZ). The only ARM926EJ-S
PXP Development Chip clock input that can function at this frequency is
PLLCLKEXT.
Also, the settings for VCO divider, output divider, and output select values are
interrelated and must be set correctly. Some combinations of settings do not result in
stable operation. For more information on the ICS clock generator and a frequency
calculator, see the ICS web site at
www.icst.com
.