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ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 4-29
[6]
b1
CFGBRIDGEMEMMAP, AMBA bridge mapping. Reserved. Must be set to 1.
[5]
b0
CFGREMAPDYEXEN, dynamic memory and expansion memory alias enable (see
Remapping of boot memory on page 4-9). When HIGH and CFGREMAPSTEXEN is LOW,
then dynamic memory is aliased to
0x00000000
. When HIGH and CFGREMAPSTEXEN is
HIGH, then expansion memory is aliased to
0x00000000
.
Note
This bit is read-only. To remap to AHB expansion memory both BOOTCSSEL[1] and
BOOTCSSEL[0] must be HIGH. The combination of CFGREMAPSTENEX LOW and
CFGREMAPDYEXEN LOW is not supported.
[4]
b1
CFGREMAPSTEXEN, static memory and expansion memory alias enable (see Remapping
of boot memory on page 4-9). When HIGH and CFGREMAPDYEXEN is LOW, then static
memory is aliased to
0x00000000
. When HIGH and CFGREMAPDYEXEN is HIGH, then
expansion memory is aliased to
0x00000000
.
Note
The combination of CFGREMAPSTENEX LOW and CFGREMAPDYEXEN LOW is not
supported.
[3]
b0
CFGMPMCnSMC, memory controller select. If this signal is HIGH, the static memory
controller is disabled. Reserved. Must be set to 0.
[2]
b1
CFGVFPENABLE, coprocessor multiplexor signal for VFP9-S. Coprocessor enable (active
HIGH).
[1]
b0
BIGENDINIT, ARM926EJ-S processor endian control. Defines the byte endian mode at
reset. When LOW, little endianness is used. When HIGH, big endianness is used.
[0]
b0
VINITHI, ARM926EJ-S processor exception location. Determines the reset location of the
exception vectors for the ARM926EJ-S.When LOW, the vectors are located at
0x0000000
.
When HIGH, the vectors are located at
0xFFFF0000
.
A convention for ARM cores is to map the exception vectors to begin at address 0. However,
the ARM926EJ-S PXP Development Chip enables the vectors to be moved to
0xFFFF0000
by
setting the V bit in coprocessor 15 register 1. To maintain compatibility across all cores, the
default reset value maps the vector to begin at address 0 (see also the ARM926EJ-S
Development Chip Reference Manual).
Table 4-9 Configuration register 2 (continued)
Bits
Power-on
reset state
Description