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Programmer’s Reference
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 4-7
Figure 4-1 on page 4-8 shows the ARM Data bus memory map. See AHB bridges and
the bus matrix on page 3-10 for details on other buses in the ARM926EJ-S PXP
Development Chip.
PCI interface bus windows
PCI SelfCfg window: 0x41000000
PCI Cfg window: 0x42000000
PCI I/O window: 0x43000000
PCI memory window 0: 0x44000000
PCI memory window 1: 0x50000000
PCI memory window 2: 0x60000000
PCI PCI3: PIC 30,
SIC 30 PCI2:
PIC 29, SIC 29
PCI1: PIC 28,
SIC 28 PCI0:
PIC 27, SIC 27
0x41000000–
0x6FFFFFFF
752MB
MPMC Chip Selects 2–3, expansion dynamic memory Expansion
memory
-
0x70000000–
0x7FFFFFFF
256MB
RealView Logic Tile expansion ( AHB M1 bus). (If a
RealView Logic Tile is installed, accesses in this range
must be decoded by the tile. This is the recommended
address range for placing memory-mapped peripherals in
a RealView Logic Tile.)
Board
(RealView
Logic Tile
headers)
PIC 21–PIC 30
(shared with
SIC)
0x80000000–
0xFFFFFFFF
2GB
a. The primary interrupt controller is in the ARM926EJ-S PXP Development Chip. The secondary controller is in the FPGA. See
Primary interrupt controller on page 4-58 and Interrupt controllers on page 4-57.
Table 4-1 Memory map (continued)
Peripheral Location
Interrupt
a
PIC
and SIC
Address
Region
size