Filter
Top Products
Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-3
3.1 ARM926EJ-S PXP Development Chip
The ARM926EJ-S PXP Development Chip and its interfaces are described in the
following sections:
• ARM926EJ-S PXP Development Chip overview
• Configuration control on page 3-7
• AHB bridges and the bus matrix on page 3-10
• AHB monitor on page 3-16
• ARM926EJ-S PXP Development Chip clocks on page 3-39
• DMA on page 3-65
• Memory interface on page 3-15
• Reset controller on page 3-22
• CLCDC interface on page 3-61
• GPIO interface on page 3-71
• UART interface on page 3-88
• Smart Card interface, SCI on page 3-81
• Synchronous Serial Port, SSP on page 3-84.
For more detail on using the ARM926EJ-S PXP Development Chip components, see
also:
• the ARM926EJ-S Development Chip Reference Manual
• AHB buses used by the FPGA and RealView Logic Tiles on page F-11
• Chapter 4 Programmer’s Reference.
3.1.1 ARM926EJ-S PXP Development Chip overview
Figure 3-1 on page 3-4 shows the main blocks of the ARM926EJ-S PXP Development
Chip.