ARM ARM DUI 0224I Computer Hardware User Manual


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Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-25
Figure 3-12 Reset signal sequence
A state machine in the FPGA (see Figure 3-13 on page 3-26) uses the value of
SYS_RESETCTL and the external reset signals to sequence the reset signals (see also,
Reset Control Register, SYS_RESETCTL on page 4-31).
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