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ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 4-57
4.11 Interrupt controllers
The PrimeCell Vectored Interrupt Controller (VIC) is an AMBA compliant SoC
peripheral that is developed, tested, and licensed by ARM Limited.
The ARM926EJ-S has two interrupt signals:
• FIQ for fast, low latency interrupt handling
• IRQ for more general interrupts.
The VIC in the ARM926EJ-S PXP Development Chip accepts interrupts from
peripherals located on the RealView Logic Tiles or in the FPGA and generates the FIQ
and IRQ signals. The VIC provides a software interface to the interrupt system and
functions as the primary interrupt controller (PIC).
A secondary interrupt controller is implemented as a custom design in the FPGA. The
output from the secondary controller is connected to the primary controller as
VICINTSOURCE31.
Interrupt sources VICINTSOURCE[30:21] are shared between the RealView Logic
Tile and peripherals located in the FPGA.
Table 4-37 VIC Primary Interrupt Controller implementation
Property Value
Location ARM926EJ-S PXP Development Chip
Memory base address
0x10140000
for PL190 VIC (primary interrupt controller)
Interrupt FIQ and IRQ
DMA NA
Release version ARM VIC PL190 r1p1
Reference documentation ARM PrimeCell Vector Interrupt Controller (PL190) Technical
Reference Manual, Primary interrupt controller on page 4-58,
and Interrupts on page 3-72).
Table 4-38 SIC implementation
Property Value
Location FPGA
Memory base address
0x10003000
Interrupt 31 on the primary interrupt controller