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ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 4-91
4.22 Synchronous Static Memory Controller, SSMC
The PrimeCell Synchronous Static Memory Controller (SSMC) is an AMBA compliant
SoC peripheral that is developed, tested, and licensed by ARM Limited.
The following key parameters are programmable for each SSMC memory bank:
• external memory width, 8, 16, or 32-bit
• burst mode operation
• write protection
• external wait control enable
• external wait polarity
• write WAIT states for static RAM devices
• read WAIT states for static RAM and ROM devices
• initial burst read WAIT state for burst devices
• subsequent burst read WAIT state for burst devices
• read byte lane enable control
• bus turn-around (idle) cycles
• output enable and write enable output delays.
For information on default values for the memory controllers, see Memory
characteristics on page 4-15.
Note
To enable write access to the NOR flash (static chip select 1), set bit 0 of SYS_FLASH
to HIGH. The default at power-on reset is LOW.
Table 4-65 SSMC implementation
Property Value
Location ARM926EJ-S PXP Development Chip
Memory base address
0x10100000
Interrupt NA
DMA NA
Release version ARM SSMC PL093 r0p0-00rel0
Reference documentation ARM PrimeCell Static Memory Controller (PL093) Technical
Reference Manual, Configuration and initialization on
page 4-9, and Memory interface on page 3-15