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Hardware Description
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. 3-7
Timers There are four 32-bit down counters that can be used to generate
interrupts at programmable intervals. A Real-Time-Clock is fed with an
external 1Hz signal.
Synchronous serial port
The SSP provides a master or slave interface for synchronous serial
communications using Motorola SPI, TI, or National Semiconductor
Microwire devices.
Smart Card interface
The Smart Card interface signals are programmable to enable support for
a Smart Card, Security Identity Module (SIM) card, or similar module.
Watchdog A Watchdog module can be used to trigger an interrupt or system reset in
the event of software failure.
3.1.2 Configuration control
The PB926EJ-S uses configuration switches and the SYS_CFGDATAx registers in the
FPGA to control configuration of the ARM926EJ-S PXP Development Chip at
power-up. In a typical product, configuration is static and the configuration signals are
tied HIGH or LOW as appropriate.
After reset, configuration can be modified by the system controller and the
configuration registers in the FPGA. For example, you can simulate a system that boots
in big-endian or with the vector table located at address
0xFFFF0000
by changing the
value of bits 0 and 1 in the SYS_CFGDATA2 register and pressing the SDC
RECONFIG button.
See Status and system control registers on page 4-17 and Configuration registers
SYS_CFGDATAx on page 4-25.