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RealView Logic Tile
ARM DUI 0224F Copyright © 2003-2007 ARM Limited. All rights reserved. F-9
HCLKM2L2F XU129 From tile RealView Logic Tile clock to multiplexor that
provides M2 clock for the FPGA.
HCLKSL2F XU130 From tile RealView Logic Tile clock to multiplexor that
provides S clock for the FPGA.
HCLKM1L2S XU131 From tile RealView Logic Tile clock to multiplexor that
provides M1 clock for the development chip.
HCLKM2L2S XU132 From tile RealView Logic Tile clock to multiplexor that
provides M2 clock for the development chip.
HCLKSL2S XU133 From tile RealView Logic Tile clock to multiplexor that
provides S clock for the development chip.
AHBMONCLK1 XU93 To tile AHB monitor clock from ARM926EJ-S PXP
Development Chip to RealView Logic Tile.
Table F-1 RealView Logic Tile clock signals (continued)
PB926EJ-S signal
RealView Logic Tile
signal (top header)
Direction Description